A state machine has a plurality of states and transitions between these states occur when a condition for transition from one state to another state is satisfied. Most of state machines within a system, operate at timings that are synchronized with the same reference clock signal, and each state machine operates to represent only one state during the same period, while mutually exchanging signals. With a state machine that branches to at least two states depending on conditions, particularly during a transition from a certain state to another state, it is customary to have one flip-flop for one state, in order to prevent any static hazard in the circuitry that forms the state machine.
A state machine without branches is equivalent to a binary counter, and it decodes states held in k numbers of flip-flops to create a number of states n that is greater than k, without causing any static hazard, in a manner similar to a well-known Gray code counter. In a circuit designed to be completely synchronous, states hazard is no problem provided that prescribed conditions are satisfied, such as the state signals of the state machine are not used as trigger signals for other circuits. In such a case, the states of k numbers of flip-flops can be decoded to create n numbers of states, where n is a larger number than k.
An example of a state transition diagram of a state machine, given in FIGS. 14 to 6 of the ISO/IEC8802-3 Standard, has been simplified and is shown as FIG. 12 herein. When a transition condition is satisfied, this state machine acquires any one of state from five states 401 to 406, via transitions 410 to 420. For example, the condition that causes the transition 412 is "link_loss_timer_done*RD=idle*link_test_rcv=false", in accordance with the standard. When that condition is satisfied when the current state is the state 401, the transition 412 is executed to switch to the state 402.
A partial extract of the state transition diagram of the state machine is shown in FIG. 13, centered on a state Y and showing only transitions to that state and transitions from that state. An example of a configuration by which the state Y is set by one flip-flop is shown in FIG. 14.
FIG. 14 shown an example in which each state is set by a single D-type flip-flop (hereinafter abbreviated to D-type F.F.). The state Y can be obtained at a Q output terminal of a D-type F.F. 501-k by inputting to a C input terminal thereof a reference clock signal 110 via a buffer 503 and inputting to a D input terminal thereof a signal that is raised by a condition of "switch to state Y and maintain that state Y". In other words, the transition to the state Y occurs when the condition "state P.times.condition a+state Q.times.condition b" occurs (see FIG. 13). In addition, to maintain the state Y when the state is currently Y, the condition is "state Y.times.(-condition c) (-condition d)", according to FIG. 13. The sum of a condition (transition condition) 111Y for transition to the state Y and a condition (holding condition) 612Y for holding the state Y is obtained by an OR gate 502-k and is input to the D input terminal of the D-type F.F. 501-k. The transition condition 111Y and the holding condition 612Y are obtained by using AND gates 504 to 507 shown in FIG. 15.
Operating waveforms of the state machine of FIG. 14 are shown in FIG. 16. The reference clock signal 110 is generated throughout all operating periods and the transition condition 111Y for transition to the state Y becomes true at a time a. At this point, either the condition a is satisfied within the state P or the condition b is satisfied within the state Q. Since the transition condition 111Y is modified by a certain delay with respect to the timing of the system clock, the state Y becomes true at a time b, which is the time of the next clock. Subsequently, a transition condition 111W for transition to the state W becomes true at a time c. At this point, a condition d is satisfied within the state Y. The holding condition 612Y for the state Y remains active in the state Y while there is no condition for the transition from the state Y. In other words, the holding condition 612Y is held true by ensuring that neither the condition c nor the condition d is satisfied during the period from the time b to the time c. The operation of the holding condition 612Y is similar to that when a condition for transition from the state Y to a sate Z is satisfied, by satisfying the condition c when in the state Y, at the time c. The state Y is made false at a time d by the transition condition 612Y going false at the time c.
An example of a configuration in which one state is set by one JK-type flip-flop (hereinafter abbreviated to JK-type F.F.) is shown in FIG. 17. The state Y can be obtained at a Q output terminal of a JK-type F.F. 521-k by inputting the reference clock signal 110 to a C input terminal thereof, the transition condition 111Y for transition to the state Y to a first input terminal thereof, and the transition condition 212Y for transition to another state from the state Y to a second input terminal thereof. The transition condition 111Y for transition to the state Y is equivalent to that for a D-type F.F., and the transition condition 212Y for transition to another state from the state Y is "state Y.times.condition c+state Y.times.condition d", according to FIG. 13. The transition condition 111Y and the transition condition 212Y are obtained by AND gates 522 to 525 and OR gates 526 and 527, as shown in FIG. 18.
Operational waveforms of the state machine of FIG. 16 are shown in FIG. 19. The transition condition 111Y for transition to the state Y becomes true at the time a. At this point, either the condition a is satisfied within the state P or the condition b is satisfied within the state Q. This makes the state Y true at the time b. The transition condition from the state Y subsequently becomes true at the time c. At this point, either the condition c is satisfied within the state Y, or the condition d is satisfied. This makes the state Y become false at the time d.
In accordance with these conventional techniques, a large number of state machines which configure the system must be operated simultaneously at the clock timing required by the system, which raises a problem in that the power consumption increases. Any increase in the number of state machines and the number of state machine's states necessitates increased number of components, and the clock is need to be driven by a corresponding amount. In addition, in order to drive the clocks of a large number of flip-flops simultaneously, a buffer component having a large drive capability is necessary. The power consumption problem is dramatic in a system in which state transition conditions occur at a far longer separation than the reference clock, such as a state machine for a link integrity test as set by the ISO/IEC8802-3 Standard and shown in FIG. 12.
In the state machine of FIG. 12, transition conditions satisfy frequently, on the order of microseconds to seconds with respect to the reference clock signal of 10 MHz. In that case, driving all of the flip-flops at the 10 MHz of the reference clock signal means that power losses are great when they are not operating.
In addition, the conventional technique necessitates that the conditions for transition to the various states and either the conditions for maintaining those states or conditions for transition to another state from those states are input the flip-flops representing the states of the state machine. This makes the state machine more complicated and necessitates a large number of circuit components. A transition condition to a certain state is also a transition condition from another state, and signals indicating similar conditions can be used in a complicated fashion to indicate other states. As a result, the redundancy of the circuitry increases, which makes the circuitry more complicated and is a factor in increasing the number of debugging and maintenance steps.
An objective of the present invention is to provide a state machine, a semiconductor device, and electronic equipment using the same, which enable a reduction in power consumption.
Another objective of the present invention is to provide a state machine, a semiconductor device, and electronic equipment using the same, which enable a reduction in circuit redundancy, simplify the circuitry accordingly, and which also enable a reduction in the number of debugging and maintenance steps therefor.